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asix electronics corporation fi rst released date : dec/13/1999 2f, no.13, industry east rd. ii, science-based industrial park, hsin-chu city, taiwan, r.o.c. tel: 886-3-579-9500 fax: 886-3-579-9558 http://www.asix.com.tw ax88196 l 10/100base fast ethernet mac controller 10/100base local cpu bus fast ethernet mac controller with embedded sram, sni interface and parallel port document no.: ax196-14 / v1.4 / nov. 21 ? 00 features ieee 802.3u 100base-t, tx, and t4 compatible single chip local cpu bus 10/100mbps fast ethernet mac controller embedded 8k * 16 bit sram ne2000 register level compatible instruction support both 8 bit and 16 bit local cpu interf ace s include mcs-51 series, 80186 series and mc68k series cpu support both 10mbps and 100mbps data rate support both full-duplex or half-duplex operation provides a mii port for both 10/100mbps operation provides sni i/f for home lan phy or 10m transceiver option support eeprom interface to store mac address external and internal loop-back capability support standard print port, can also used as general i/o port 128-pin lqfp low profile package 20mhz to 2 5mhz operation, dual 5v and 3.3 v cmos process with 5v i/o tolerance . or pure 3.3v operation *ieee is a registered trademark of the institute of electrical and electronic engineers, inc. *all other trademarks and registered trademark are the property of their respective holders. product description the ax88196 fast ethernet controller is a high performance and highly integrated local cpu bus ethernet controller with embedded 8k*16 bit sram. the ax88196 supports both 8 bit and 16 bit local cpu interf ace s include mcs-51 series, 80186 series, mc68k series cpu and isa bus. the ax88196 implements both 10mbps and 100mbps ethernet function based on ieee802.3 / ieee802.3u lan standard and supports both 10mbps/100mbps media-independent interface (mii) and legacy pure 10mbps sni interface to simplify the design. using serial network interface (sni) transceiver, home lan phy or 10base-2 bnc type media can be supported. as well as, the chip also provides standard print port (parallel port interface), can be used for printer server device or treat as simple general i/o port. system block diagram always contact asix for possible updates before starting a design. this data sheet contains new products information. asix electronics reserves the rights to modify product specification without notice. no liability is assumed as a result of the use of this product. no rights under any patent accompany the sale of the product. 8051 cpu latch ax88196 ad bus addr l addr h ctl bus 10/100m phy/txrx rj45 home lan phy or 10m phy/txrx rj11 or bnc print port or general i/o ports
ax88196 local cpu bus mac controller asix electronics corporation 2 contents 1.0 introduction ................................ ................................ ................................ ................................ ............... 4 1.1 g eneral d escription : ................................ ................................ ................................ ................................ ..... 4 1.2 ax88196 b lock d iagram : ................................ ................................ ................................ ............................... 4 1.3 ax88196 p in c onnection d iagram ................................ ................................ ................................ ................ 5 1.3.1 ax88196 pin connection diagram for isa bus mode ................................ ................................ ................. 6 1.3.2 ax88196 pin connection diagram for 80x86 mode ................................ ................................ .................... 7 1.3.3 ax88196 pin connection diagram for mc68k mode ................................ ................................ ................. 8 1.3.4 ax88196 pin connection diagram for mcs-51 mode ................................ ................................ ................ 9 2.0 signal description ................................ ................................ ................................ ................................ .. 10 2.1 l ocal cpu b us i nterface s ignals g roup ................................ ................................ ................................ .... 10 2.2 mii interface signals group ................................ ................................ ................................ ........................ 11 2.3 eeprom s ignals g roup ................................ ................................ ................................ ............................... 12 2.4 sni i nterface pins group ................................ ................................ ................................ .............................. 12 2.5 s tandard p rinter p ort i nterface pins group ................................ ................................ ............................. 12 2.6 p ower on configuration setup signals pins group ................................ ................................ ..................... 13 2.7 m iscellaneous pins group ................................ ................................ ................................ ............................ 13 3.0 memory and i/o mapping ................................ ................................ ................................ ...................... 15 3.1 eeprom m emory m apping ................................ ................................ ................................ .......................... 15 3.2 i/o m apping ................................ ................................ ................................ ................................ .................... 15 3.3 sram m emory m apping ................................ ................................ ................................ ............................... 15 4.0 registers operation ................................ ................................ ................................ .............................. 16 4.1 c ommand r egister (cr) o ffset 00h (r ead /w rite ) ................................ ................................ ................... 18 4.2 i nterrupt s tatus r egister (isr) o ffset 07h (r ead /w rite ) ................................ ................................ ...... 18 4.3 i nterrupt mask register (imr) o ffset 0fh (w rite ) ................................ ................................ .................. 19 4.4 d ata c onfiguration r egister (dcr) o ffset 0eh (w rite ) ................................ ................................ ........ 19 4.5 t ransmit c onfiguration r egister (tcr) o ffset 0dh (w rite ) ................................ ................................ . 19 4.6 t ransmit s tatus r egister (tsr) o ffset 04h (r ead ) ................................ ................................ ................. 20 4.7 r eceive c onfiguration (rcr) o ffset 0ch (w rite ) ................................ ................................ ................... 20 4.8 r eceive s tatus r egister (rsr) o ffset 0ch (r ead ) ................................ ................................ ................... 20 4.9 i nter - frame gap (ifg) o ffset 16h (r ead /w rite ) ................................ ................................ ....................... 21 4.10 i nter - frame gap s egment 1(ifgs1) o ffset 12h (r ead /w rite ) ................................ ................................ 21 4.11 i nter - frame gap s egment 2(ifgs2) o ffset 13h (r ead /w rite ) ................................ ................................ 21 4.12 mii/eeprom m anagement r egister (memr) o ffset 14h (r ead /w rite ) ................................ ............... 21 4.13 t est r egister (tr) o ffset 15h (w rite ) ................................ ................................ ................................ .... 21 4.14 spp d ata p ort r egister (spp_dpr) o ffset 18h (r ead /w rite ) ................................ ............................... 22 4.15 spp s tatus p ort r egister (spp_spr) o ffset 19h (r ead ) ................................ ................................ ........ 22 4.16 spp c ommand p ort r egister (spp_cpr) o ffset 1ah (r ead /w rite ) ................................ ...................... 22 5.0 cpu i/o read and write functions ................................ ................................ ................................ .. 23 5.1 isa bus type access functions . ................................ ................................ ................................ .................... 23 5.2 80186 cpu bus type access functions . ................................ ................................ ................................ ........ 23 5.3 mc68k cpu bus type access functions . ................................ ................................ ................................ ...... 24 5.4 mcs-51 cpu bus type access functions . ................................ ................................ ................................ ..... 24 6.0 electrical specification and timings ................................ ................................ ....................... 25 6.1 a bsolute m aximum r atings ................................ ................................ ................................ ......................... 25 6.2 g eneral o peration c onditions ................................ ................................ ................................ ................... 25 6.3 dc c haracteristics ................................ ................................ ................................ ................................ ...... 25 6.4 a.c. t iming c haracteristics ................................ ................................ ................................ ........................ 26 6.4.1 xtal / clock ................................ ................................ ................................ ................................ ......... 26
ax88196 local cpu bus mac controller asix electronics corporation 3 6.4.2 reset timing ................................ ................................ ................................ ................................ ............. 26 6.4.3 isa bus access timing ................................ ................................ ................................ .............................. 27 6.4.4 80186 type i/o access timing ................................ ................................ ................................ .................. 28 6.4.5 68k type i/o access timing ................................ ................................ ................................ ..................... 29 6.4.6 8051 bus access timing ................................ ................................ ................................ ........................... 30 6.4.7 mii timing ................................ ................................ ................................ ................................ ................ 31 6.4.8 sni timing ................................ ................................ ................................ ................................ ................ 32 7.0 package information ................................ ................................ ................................ ........................... 33 appendix a: application note ................................ ................................ ................................ ................. 34 a.1 u sing c rystal 25mh z or 20mh z ................................ ................................ ................................ ................. 34 a.2 u sing o scillator 25mh z or 20mh z ................................ ................................ ................................ ............ 34 a.3 u sing 60mh z o scillator /c rystal ................................ ................................ ................................ .............. 34 a.4 d ual power (5v and 3.3v/3.0v) application ................................ ................................ .............................. 35 a.5 s ingle power (3.3v/3.0v) application ................................ ................................ ................................ ......... 35 a.6 d ual power (5v and 3.3v) application with 3.3v phy ................................ ................................ ............. 36 errata of ax88196 version ed2 ................................ ................................ ................................ ................. 37 demonstration circuit : ax88196 + ethernet phy + homepna 1m8 phy .............................. 38 figures f ig - 1 ax88196 b lock d iagram ................................ ................................ ................................ .............................. 4 f ig - 2 ax88196 p in c onnection d iagram ................................ ................................ ................................ ............... 5 f ig - 3 ax88196 p in c onnection d iagram for isa b us m ode ................................ ................................ ................ 6 f ig - 4 ax88196 p in c onnection d iagram for 80 x 86 m ode ................................ ................................ ................... 7 f ig - 5 ax88196 p in c onnection d iagram for mc68k m ode ................................ ................................ ................ 8 f ig - 6 ax88196 p in c onnection d iagram for mcs-51 m ode ................................ ................................ ................ 9 tables t ab - 1 l ocal cpu bus interface signals group ................................ ................................ ................................ ... 11 t ab - 2 mii interface signals group ................................ ................................ ................................ ...................... 11 t ab - 3 eeprom bus interface signals group ................................ ................................ ................................ ...... 12 t ab - 4 s erial n etwork i nterface pins group ................................ ................................ ................................ ...... 12 t ab - 5 s tandard p rinter p ort i nterface pins group ................................ ................................ .......................... 13 t ab - 6 p ower on configuration setup pins group ................................ ................................ ................................ 13 t ab - 7 m iscellaneous pins group ................................ ................................ ................................ .......................... 14 t ab - 8 i/o a ddress m apping ................................ ................................ ................................ ................................ .. 15 t ab - 9 l ocal m emory m apping ................................ ................................ ................................ ............................. 15 t ab - 10 p age 0 of mac c ore r egisters m apping ................................ ................................ ................................ . 16 t ab - 11 p age 1 of mac c ore r egisters m apping ................................ ................................ ................................ . 17
ax88196 local cpu bus mac controller asix electronics corporation 4 1.0 introduction 1.1 general description: the ax88196 provides industrial standard ne2000 registers level compatable instruction set. various drivers are easy acquired, maintenance and usage. no much additional effort to be paid. software is easily port to various embedded system with no pain and tears the ax88196 fast ethernet controller is a high performance and highly integrated local cpu bus ethernet controller with embedded 8k*16 bit sram. the ax88196 supports both 8 bit and 16 bit local cpu interf ace s include mcs-51 series, 80186 series, mc68k series cpu and isa bus. the ax88196 implements both 10mbps and 100mbps ethernet function based on ieee802.3 / ieee802.3u lan standard and supports both 10mbps/100mbps media-independent interface (mii) and legacy pure 10mbps sni interface to simplify the design. using serial network interface (sni) transceiver, home lan phy or 10base-2 bnc type media can be supported. as well as, the chip also provides standard print port ( parallel port interface ), can be used for printer server device or treat as simple general i/o port. the main difference between ax88196 and ax88195 are : 1) replace memory i/f with sni and spp i/f. 2) canceling sax address decoding. 3) fix interrupt status can ? t always clean up problem of ax88195. ax88196 use 128-pin lqfp low profile package, 2 5mhz o peration, dual 5v and 3.3 v cmos process with 5v i/o tolerance or pure 3.3v operation. 1.2 ax88196 block diagram: fig - 1 ax88196 block diagram mac core 8k* 16 sram and memory arbiter remote dma fifos ne2000 registers host interface sta seeprom i/f sd[15:0] sa[9:0] ctl bus mii i/f eecs eeck eedi eedo sni i/f spp / gio print port or general i/o smdc smdio
ax88196 local cpu bus mac controller asix electronics corporation 5 1.3 ax88196 pin connection diagram the ax88196 is housed in the 128-pin plastic light quad flat pack. fig - 2 ax88196 pin connection diagram shows the ax88196 pin connection diagram. fig - 2 ax88196 pin connection diagram 123 118 122 78 70 54 41 32 24 12 8 lvdd 117 75 57 42 26 31 21 sa[1] vss 107 105 66 65 63 60 25 16 13 3 7 vss lclk/xtalin 128 115 112 61 33 111 43 19 15 4 109 106 77 62 11 6 71 49 17 lvdd 68 58 56 55 45 23 vss 53 116 113 59 36 34 1 vss 124 108 hvdd 28 22 9 hvdd nc 126 119 110 121 79 74 80 72 46 29 52 10 67 44 39 27 51 5 127 125 120 114 73 69 38 48 76 47 35 30 20 2 vss vss 40 37 50 18 14 ax88196 local cpu bus 10/100base mac controller 103 104 82 91 81 86 93 94 84 87 95 96 90 88 92 85 89 83 98 97 99 100 102 101 vss lvdd sd[0] sd[1] sd[2] sd[3] sa[0] sa[3] sa[2] sa[5] sa[4] sa[6] sa[7] sa[9] sa[8] /iowr sd[15] sd[14] sd[13] sd[12] sd[11] sd[10] sd[9] sd[8] sd[6] sd[4] sd[5] sd[7] reset /bhe txd[1] txd[2] txd[3] xtalout eedi eedo eeck eecs /reset rdy/dtack irq /cs sal[0] sal[1] sal[2] sah[1] sah[2] /iocs16 aen/psen /iord r/w /lds /uds 64 clko sah[0] nc nc nc /irq hvdd pd0 /err slct pe /ack busy /strb /atfd /init /slin lvdd lvdd vss vss io_base[2] io_base[1] pd1 pd2 pd3 pd4 pd5 pd6 pd7 scrs tx_en tx_clk mdc mdio rxd[3] rxd[2] rxd[1] rxd[0] rx_clk crs col rx_dv srxd srxc /slink stxe stxd stxc scol rx_er txd[0] vss vss vss hvdd io_base[0] cpu[1] cpu[0] nc test nc nc nc nc /clk_div3
ax88196 local cpu bus mac controller asix electronics corporation 6 1.3.1 ax88196 pin connection diagram for isa bus mode fig - 3 ax88196 pin connection diagram for isa bus mode 123 118 122 78 70 54 41 32 24 12 8 lvdd 117 75 57 42 26 31 21 sa[1] vss 107 105 66 65 63 60 25 16 13 3 7 vss lclk/xtalin 128 115 112 61 33 111 43 19 15 4 109 106 77 62 11 6 71 49 17 lvdd 68 58 56 55 45 23 vss 53 116 113 59 36 34 1 vss 124 108 hvdd 28 22 9 hvdd nc 126 119 110 121 79 74 80 72 46 29 52 10 67 44 39 27 51 5 127 125 120 114 73 69 38 48 76 47 35 30 20 2 vss vss 40 37 50 18 14 ax88196 local cpu bus 10/100base mac controller (for isa bus i/f) 103 104 82 91 81 86 93 94 84 87 95 96 90 88 92 85 89 83 98 97 99 100 102 101 vss lvdd sd[0] sd[1] sd[2] sd[3] sa[0] sa[3] sa[2] sa[5] sa[4] sa[6] sa[7] sa[9] sa[8] /iowr sd[15] sd[14] sd[13] sd[12] sd[11] sd[10] sd[9] sd[8] sd[6] sd[4] sd[5] sd[7] reset /bhe txd[1] txd[2] txd[3] xtalout eedi eedo eeck eecs /reset rdy irq /cs sal[0] sal[1] sal[2] sah[1] sah[2] /iocs16 aen /iord 64 clko sah[0] nc nc nc hvdd pd0 /err slct pe /ack busy /strb /atfd /init /slin lvdd lvdd vss vss io_base[2] io_base[1] pd1 pd2 pd3 pd4 pd5 pd6 pd7 scrs tx_en tx_clk mdc mdio rxd[3] rxd[2] rxd[1] rxd[0] rx_clk crs col rx_dv srxd srxc /slink stxe stxd stxc scol rx_er txd[0] vss vss vss hvdd io_base[0] cpu[1] cpu[0] nc test nc nc nc nc /clk_div3
ax88196 local cpu bus mac controller asix electronics corporation 7 1.3.2 ax88196 pin connection diagram for 80x86 mode fig - 4 ax88196 pin connection diagram for 80x86 mode 123 118 122 78 70 54 41 32 24 12 8 lvdd 117 75 57 42 26 31 21 sa[1] vss 107 105 66 65 63 60 25 16 13 3 7 vss lclk/xtalin 128 115 112 61 33 111 43 19 15 4 109 106 77 62 11 6 71 49 17 lvdd 68 58 56 55 45 23 vss 53 116 113 59 36 34 1 vss 124 108 hvdd 28 22 9 hvdd nc 126 119 110 121 79 74 80 72 46 29 52 10 67 44 39 27 51 5 127 125 120 114 73 69 38 48 76 47 35 30 20 2 vss vss 40 37 50 18 14 ax88196 local cpu bus 10/100base mac controller (for x86 interface) 103 104 82 91 81 86 93 94 84 87 95 96 90 88 92 85 89 83 98 97 99 100 102 101 vss lvdd sd[0] sd[1] sd[2] sd[3] sa[0] sa[3] sa[2] sa[5] sa[4] sa[6] sa[7] sa[9] sa[8] /iowr sd[15] sd[14] sd[13] sd[12] sd[11] sd[10] sd[9] sd[8] sd[6] sd[4] sd[5] sd[7] reset /bhe txd[1] txd[2] txd[3] xtalout eedi eedo eeck eecs /reset rdy irq /cs sal[0] sal[1] sal[2] sah[1] sah[2] /iord 64 clko sah[0] nc nc nc hvdd pd0 /err slct pe /ack busy /strb /atfd /init /slin lvdd lvdd vss vss io_base[2] io_base[1] pd1 pd2 pd3 pd4 pd5 pd6 pd7 scrs tx_en tx_clk mdc mdio rxd[3] rxd[2] rxd[1] rxd[0] rx_clk crs col rx_dv srxd srxc /slink stxe stxd stxc scol rx_er txd[0] vss vss vss hvdd io_base[0] cpu[1] cpu[0] nc test nc nc nc nc /clk_div3 nc nc
ax88196 local cpu bus mac controller asix electronics corporation 8 1.3.3 ax88196 pin connection diagram for mc68k mode fig - 5 ax88196 pin connection diagram for mc68k mode 123 118 122 78 70 54 41 32 24 12 8 lvdd 117 75 57 42 26 31 21 sa[1] vss 107 105 66 65 63 60 25 16 13 3 7 vss lclk/xtalin 128 115 112 61 33 111 43 19 15 4 109 106 77 62 11 6 71 49 17 lvdd 68 58 56 55 45 23 vss 53 116 113 59 36 34 1 vss 124 108 hvdd 28 22 9 hvdd nc 126 119 110 121 79 74 80 72 46 29 52 10 67 44 39 27 51 5 127 125 120 114 73 69 38 48 76 47 35 30 20 2 vss vss 40 37 50 18 14 ax88196 local cpu bus 10/100base mac controller (for 68k interface) 103 104 82 91 81 86 93 94 84 87 95 96 90 88 92 85 89 83 98 97 99 100 102 101 vss lvdd sd[0] sd[1] sd[2] sd[3] sa[3] sa[2] sa[5] sa[4] sa[6] sa[7] sa[9] sa[8] sd[15] sd[14] sd[13] sd[12] sd[11] sd[10] sd[9] sd[8] sd[6] sd[4] sd[5] sd[7] reset txd[1] txd[2] txd[3] xtalout eedi eedo eeck eecs /reset /dtack /cs sal[0] sal[1] sal[2] sah[1] sah[2] r/w /lds /uds 64 clko sah[0] nc nc nc /irq hvdd pd0 /err slct pe /ack busy /strb /atfd /init /slin lvdd lvdd vss vss io_base[2] io_base[1] pd1 pd2 pd3 pd4 pd5 pd6 pd7 scrs tx_en tx_clk mdc mdio rxd[3] rxd[2] rxd[1] rxd[0] rx_clk crs col rx_dv srxd srxc /slink stxe stxd stxc scol rx_er txd[0] vss vss vss hvdd io_base[0] cpu[1] cpu[0] nc test nc nc nc nc /clk_div3 nc nc nc
ax88196 local cpu bus mac controller asix electronics corporation 9 1.3.4 ax88196 pin connection diagram for mcs-51 mode fig - 6 ax88196 pin connection diagram for mcs-51 mode 123 118 122 78 70 54 41 32 24 12 8 lvdd 117 75 57 42 26 31 21 sa[1] vss 107 105 66 65 63 60 25 16 13 3 7 vss lclk/xtalin 128 115 112 61 33 111 43 19 15 4 109 106 77 62 11 6 71 49 17 lvdd 68 58 56 55 45 23 vss 53 116 113 59 36 34 1 vss 124 108 hvdd 28 22 9 hvdd nc 126 119 110 121 79 74 80 72 46 29 52 10 67 44 39 27 51 5 127 125 120 114 73 69 38 48 76 47 35 30 20 2 vss vss 40 37 50 18 14 ax88196 local cpu bus 10/100base mac controller (for mcs-51 interface) 103 104 82 91 81 86 93 94 84 87 95 96 90 88 92 85 89 83 98 97 99 100 102 101 vss lvdd sd[0] sd[1] sd[2] sd[3] sa[0] sa[3] sa[2] sa[5] sa[4] sa[6] sa[7] sa[9] sa[8] /iowr sd[6] sd[4] sd[5] sd[7] reset txd[1] txd[2] txd[3] xtalout eedi eedo eeck eecs /reset /cs sal[0] sal[1] sal[2] sah[1] sah[2] /psen /iord 64 clko sah[0] nc nc nc /irq hvdd pd0 /err slct pe /ack busy /strb /atfd /init /slin lvdd lvdd vss vss io_base[2] io_base[1] pd1 pd2 pd3 pd4 pd5 pd6 pd7 scrs tx_en tx_clk mdc mdio rxd[3] rxd[2] rxd[1] rxd[0] rx_clk crs col rx_dv srxd srxc /slink stxe stxd stxc scol rx_er txd[0] vss vss vss hvdd io_base[0] cpu[1] cpu[0] nc test nc nc nc nc /clk_div3 nc nc nc nc nc nc nc nc nc nc nc
ax88196 local cpu bus mac controller asix electronics corporation 10 2.0 signal description the following terms describe the ax88196 pin-out: all pin names with the ? / ? suffix are asserted low. the following abbreviations are used in following tables . i input pu pull up o output pd pull down i/o input/output p power pin od open drain 2.1 local cpu bus i nterface s ignals g roup signal type pin no. description sal [2:0] i/pd 113 ? 111 system address select low : signals sa l [2:0] are additional address signal input lines which active low enable higher i/o address decoder on c hip . sah [2:0] i/pu 116 ? 114 system address select high : signals sa h [2:0] are additional address signal input lines which active high enable higher i/o address decoder on c hip . sa [9:1] , sa [0] /uds i 10 ? 1 system address : signals sa[9:0] are address bus input lines which lower i/o spaces on c hip . sa[0] also means upper data strobe (/uds) active low signal in 68k application mode /bhe or /lds i 18 bus high enable or lower data strobe : bus high enable is active low signal in some 16 bit application mode which enable high bus (sd[15:8]) active. the signal also name as lower data strobe (lds) for 68k application mode. sd[15:0] i/o 20 ? 23, 25 ? 28, 30 ? 33, 35 ? 38 system data bus : signals sd[15:0] constitute the bi-directional data bus. ireq/ ireq o 12 interrupt request : when isa bus or 80186 cpu mode is select. ireq is asserted high to indicate the host system that the chip requires host software service. when mc68k or mcs-51 cpu mode is select. / ireq is asserted low to indicate the host system that the chip requires host software service. rdy/dtack o d 125 ready : this signal is set low to insert wait states during remote dma transfer. /dtack : when motorola cpu type is select, the pin is active low inform cpu that data is accepted. /cs i 123 chip select when the /cs signal is asserted, the chip is selected . / iord i 15 i/o read : the host asserts / iord to read data from ax88196 i/o space. when motorola cpu type is select , the pin is useless. / iowr or r/w i 14 i/o write : the host asserts / iowr to write data into ax88196 i/o space. when motorola cpu type is select, the pin is active high for read operation at the same time. / ocs16 o d 120 i/o is 16 bit port : the /io is16 is asserted when the address at the range corresponds to an i/o address to which the c hip responds, and the i/o port addressed is capable of 16-bit access.
ax88196 local cpu bus mac controller asix electronics corporation 11 aen or /psen i /pd 124 address enable : the signal is asserted when the address bus is available for dma cycle. when negated (low), ax88196 an i/o slave device may respond to addresses and i/o command . psen : this signal is active low for 8051 program access. for i/o device, ax88196, this signal is active high to access the chip. this signal is for 8051 bus application only. tab - 1 local cpu b us interface signals group 2.2 mii interface signals group signal type pin no. description rxd[3:0] i 90 ? 87 receive data : rxd[3:0] is driven by the phy synchronously with respect to rx_clk. crs i 85 carrier sense : asynchronous signal crs is asserted by the phy when either the transmit or receive medium is non-idle. rx_dv i 83 receive data valid : rx_dv is driven by the phy synchronously with respect to rx_clk. asserted high when valid data is present on rxd [3:0]. rx_er i 82 receive error : rx_er ,is driven by phy and synchronous to rx_clk, is asserted for one or more rx_clk periods to indicate to the port that an error has detected. rx_clk i 86 receive clock : rx_clk is a continuous clock that provides the timing reference for the transfer of the rx_dv,rxd[3:0] and rx_er signals from the phy to the mii port of the repeater. col i 84 collision : this signal is driven by phy when collision is detected. tx_en o 95 transmit enable : tx_en is transition synchronously with respect to the rising edge of tx_clk. tx_en indicates that the port is presenting nibbles on txd [3:0] for transmission. txd[3:0] o 99 ? 96 transmit data : txd[3:0] is transition synchronously with respect to the rising edge of tx_clk. for each tx_clk period in which tx_en is asserted, txd[3:0] are accepted for transmission by the phy. tx_clk i 94 transmit clock : tx_clk is a continuous clock from phy. it provides the timing reference for the transfer of the tx_en and txd[3:0] signals from the mii port to the phy. mdc o 92 station management data clock : the timing reference for mdio. all data transfers on mdio are synchronized to the rising edge of this clock. mdc is a 2.5mhz frequency clock output. mdio i/o/pu 91 station management data input / output : serial data input/output transfers from/to the phys . the transfer protocol conforms to the ieee 802.3u mii specification. tab - 2 mii interface signals group
ax88196 local cpu bus mac controller asix electronics corporation 12 2.3 eeprom s ignals g roup signal type pin no. description eecs o 106 eeprom chip select : eeprom chip select signal. eeck o 107 eeprom clock : signal connected to eeprom clock pin. eedi o 108 eeprom data in : signal connected to eeprom data input pin. eedo i /pu 109 eeprom data out : signal connected to eeprom data output pin. tab - 3 eeprom bus interface signals group 2.4 s ni interface pins group signal type pin no. description stxc i 66 transmit clock : this signal is driven by phy with 20mhz clock. stxd o 68 transmit data : stxd is transition synchronously with respect to the rising edge of stxc. for each stxc period in which stxe is asserted, stxd is accepted for transmission by the phy. stxe o 70 transmit enable : stxe is transition synchronously with respect to the rising edge of stxc. stxe indicates that the port is presenting data on stxd for transmission. scol i 76 collision : this signal is driven by phy when collision is detected. srxc i 78 receive clock : srxc is driven by phy for received data synchronization. srxd i 79 receive data : srxd is driven by the phy synchronously with respect to srxc. scrs i 80 carrier sense : asynchronous signal scrs is asserted by the phy when either the transmit or receive medium is non-idle. /slink i/pu 74 link indicator : active low indicate the sni interface is link to network. when sni is not used must keep the pin no connection or pull high the signal. tab - 4 serial network interface pins group 2.5 s tandard printer port interface pins group signal type pin no. description pd[7:0] i/ o /pu 52, 53 55-58 60, 61 parallel data :the bi-directional parallel data bus is used to transfer information between cpu and peripherals. default serve as input, using /doe bit of register offset x1ah to set the direction. busy i 46 busy : this is a status input from the printer, high indicating that the printer is not ready to receive new data. /ack i 47 acknowledge : a low active input from the printer indicating that it has received the data and is ready to accept new data. pe i 48 paper empty : a status input from the printer, high indicating that the printer is out of paper. slct i 50 slect : this high active input from the printer indicating that it has power on. /err i 51 error : a low active input from the printer indicating that there is an error condition at the printer. /slctin o 41 slect in : this active low output selects the printer. /init o 42 init : this signal is used to initiate the printer when low. /atfd o 43 auto feed :this output goes low to cause the printer to automatically
ax88196 local cpu bus mac controller asix electronics corporation 13 feed one line after each line is printed. /strb o 45 strobe : a low active pulse on this output is used to strobe the print data into the printer. tab - 5 standard printer port interface pins group 2.6 power on configuration setup signals pins group signal type pin no. description io_base[2:0] i /pu 62, 63,65 io_base[2] io_base[1] io_base[0] io_base 0 0 0 300h 0 0 1 320h 0 1 0 340h 0 1 1 360h 1 0 0 380h 1 0 1 3a0h 1 1 0 200h 1 1 1 220h cpu[1:0] i/pu 71, 72 cpu[1] cpu[0] cpu type 0 0 isa bus 0 1 80186 1 0 mc68k 1 1 mcs-51 (805x) tab - 6 power on configuration setup pins group 2.7 miscellaneous pins group signal type pin no. description lclk/xtalin i 103 cmos local clock : a 25mhz clock, +/- 100 ppm, 40%-60% duty cycle. crystal oscillator input : a 25mhz crystal, +/- 25 ppm can be connected across xtalin and xtalout. xtalout o 104 crystal oscillator output : a 25mhz crystal, +/- 25 ppm can be connected across xtalin and xtalout. if a single-ended external clock (lclk) is connected to xtalin, the crystal output pin should be left floating. clko o 101 clock output : this clock is source from lclk/xtalin. /clk_div3 i/pu 67 clock devide 3 enable : active low to enable the devided 3 circuit. that internally devides lclk/xtalin input frequeny by 3 and then feed into internal circuit for system clock used. default value set to logic high, this function is disabled. reset i /pd 127 reset : reset is active high then place ax88196 into reset mode immediately. during falling edge the ax88196 loads the power on setting data. user can select either reset or /reset for applications. / reset i /pu 126 / reset : reset is active low then place ax88196 into reset mode immediately. during ris ing edge the ax88196 loads the power on setting data. user can select either reset or /reset for applications. /test i/pu 77 test pin : active low the pin is just for test mode setting purpose only. must be pull high when normal operation. nc n/a 13, 16, 17, 39, 73, 117, no connection : for manufacturing test only.
ax88196 local cpu bus mac controller asix electronics corporation 14 118, 121, 122 lvdd p 44, 54, 100, 110, 128 power supply : +3.3v dc. hvdd p 19, 29, 64, 75 power supply : +5v dc. note : for pure 3.3v single power solution, all the hvdd pin can connect to +3.3v. care should be taken that hvdd input power must be greater or equal ( > = ) than lvdd. vss p 11, 24, 34, 40, 49,59, 69, 81,93, 102, 105, 119 power supply : +0v dc or ground power. tab - 7 miscel laneous pins group
ax88196 local cpu bus mac controller asix electronics corporation 15 3.0 memory and i/o mapping there are four memory or i/o mapping used in ax88196. 1. eeprom memory mapping 2. i/o mapping 3. local memory mapping 3.1 eeprom memory mapping user can define by themselves and can access via i/o address offset 14h mii/eeprom registers 3.2 i/o mapping system i/o offset function 00 00 h 001fh mac core register tab - 8 i/o address mapping 3.3 sram memory mapping offset function 4000h 7fff ne2000 compatable mode 8 k x 16 sram buffer tab - 9 local memory mapping
ax88196 local cpu bus mac controller asix electronics corporation 16 4.0 registers operation all registers of mac core are 8-bit wide and mapped into pages which are selected by ps in the command register. page 0 (ps 1 =0 ,ps0=0 ) offset read write 00h command register ( cr ) command register ( cr ) 01h page start register ( pstart ) page start register ( pstart ) 02h page stop register ( pstop ) page stop register ( pstop ) 03h boundary pointer ( bnry ) boundary pointer ( bnry ) 04h transmit status register ( tsr ) transmit page start address ( tpsr ) 05h number of collisions register ( ncr ) transmit byte count register 0 ( tbcr0 ) 06h current page register ( cpr ) transmit byte count register 1 ( tbcr1 ) 07h interrupt status register ( isr ) interrupt status register ( isr ) 08h current remote dma address 0 ( crda0 ) remote start address register 0 ( rsar0 ) 09h current remote dma address 1 ( crda1 ) remote start address register 1 ( rsar1 ) 0ah reserved remote byte count 0 ( rbcr0 ) 0bh reserved remote byte count 1 ( rbcr1 ) 0ch receive status register ( rsr ) receive configuration register ( rcr ) 0dh frame alignment errors ( cntr0 ) transmit configuration register ( tcr ) 0eh crc errors ( cntr1 ) data configuration register ( dcr ) 0fh missed packet errors ( cntr2 ) interrupt mask register ( imr ) 10h , 11h data port data port 12h ifgs1 ifgs1 13h ifgs2 ifgs2 14h mii/eeprom access mii/eeprom access 15h - test register 16h inter-frame gap ( ifg ) inter-frame gap ( ifg ) 17h reserved reserved 18h - 1ah standard printer port (spp) standard printer port (spp) 1bh - 1eh reserved reserved 1fh reset reserved tab - 10 page 0 of mac core registers mapping
ax88196 local cpu bus mac controller asix electronics corporation 17 page 1 ( ps1=0, ps 0 =1) offset read write 00h command register ( cr ) command register ( cr ) 01h physical address register 0 ( para0 ) physical address register 0 ( par0 ) 02h physical address register 1 ( para1 ) physical address register 1 ( par1 ) 03h physical address register 2 ( para2 ) physical address register 2 ( par2 ) 04h physical address register 3 ( para3 ) physical address register 3 ( par3 ) 05h physical address register 4 ( para4 ) physical address register 4 ( par4 ) 06h physical address register 5 ( para5 ) physical address register 5 ( par5 ) 07h current page register ( cpr ) current page register ( cpr ) 08h multicast address register 0 ( mar0 ) multicast address register 0 ( mar0 ) 09h multicast address register 1 ( mar1 ) multicast address register 1 ( mar1 ) 0ah multicast address register 2 ( mar2 ) multicast address register 2 ( mar2 ) 0bh multicast address register 3 ( mar3 ) multicast address register 3 ( mar3 ) 0ch multicast address register 4 ( mar4 ) multicast address register 4 ( mar4 ) 0dh multicast address register 5 ( mar5 ) multicast address register 5 ( mar5 ) 0eh multicast address register 6 ( mar6 ) multicast address register 6 ( mar6 ) 0fh multicast address register 7 ( mar7 ) multicast address register 7 ( mar7 ) 10h , 11h data port data port 12h inter-frame gap segment 1 ifgs1 inter-frame gap segment 1 ifgs1 13h inter-frame gap segment 2 ifgs2 inter-frame gap segment 2 ifgs2 14h mii/eeprom access mii/eeprom access 15h - test register 16h inter-frame gap ( ifg ) inter-frame gap ( ifg ) 17h reserved reserved 18h - 1ah standard printer port (spp) standard printer port (spp) 1bh - 1eh reserved reserved 1fh reset reserved tab - 11 page 1 of mac core registers mapping
ax88196 local cpu bus mac controller asix electronics corporation 18 4.1 command register (cr) offset 00h (read/write) field name description 7 :6 ps 1,ps0 ps 1,ps0 : page select the two bit selects which register page is to be accessed. ps1 ps0 0 0 page 0 0 1 page 1 5:3 rd2,rd1 ,rd0 rd2,rd1,rd0 : remote dma command these three encoded bits control operation of the remote dma channel. rd2 could be set to abort any remote dma command in process. rd2 is reset by ax88196 when a remote dma has been completed. the remote byte count should be cleared when a remote dma has been aborted. the remote start address are not restored to the starting address if the remote dma is aborted. rd2 rd1 rd0 0 0 0 not allowed 0 0 1 remote read 0 1 0 remote write 0 1 1 not allowed 1 x x abort / complete remote dma 2 txp txp : transmit packet this bit could be set to initiate transmission of a packet 1 start start : this bit is used to active ax88196 operation. 0 stop stop : stop ax88196 this bit is used to stop the ax88196 operation. 4.2 interrupt status register (isr) offset 07h (read/write) field name description 7 rst reset status : set when ax88196 enters reset state and cleared when a start command is issued to the cr. writing to this bit is no effect. 6 rdc remote dma complete set when remote dma operation has been completed 5 cnt counter overflow set when msb of one or more of the tally counters has been set. 4 ovw overwrite : set when receive buffer ring storage resources have been exhausted. 3 txe transmit error set when packet transmitted with one or more of the following errors n excessive collisions n fifo underrun 2 rxe receive error indicates that a packet was received with one or more of the following errors crc error frame alignment error fifo overrun missed packet 1 ptx packet transmitted indicates packet transmitted with no error 0 prx packet received indicates packet received with no error.
ax88196 local cpu bus mac controller asix electronics corporation 19 4.3 interrupt mask register (imr) offset 0fh (write) field name description 7 - reserved 6 rdce dma complete interrupt enable. default ? low ? disabled. 5 cnte counter overflow interrupt enable. default ? low ? disabled. 4 ovwe overwrite interrupt enable. default ? low ? disabled. 3 txee transmit error interrupt enable. default ? low ? disabled. 2 rxee receive error interrupt enable. default ? low ? disabled. 1 ptxe packet transmitted interrupt enable. default ? low ? disabled. 0 prxe packet received interrupt enable. default ? low ? disabled. 4.4 data configuration register ( dcr ) offset 0eh (write) field name description 7 rdcr remote dma always completed 6:2 - reserved 1 bos byte order select 0: ms byte placed on ad15:ad8 and ls byte on ad7-ad0 (80186). 1: ms byte placed on ad7::ad0 and ls byte on ad15:ad0(mc68k) 0 wts word transfer select 0 : selects byte-wide dma transfers. 1 : selects word-wide dma transfers. 4.5 transmit configuration register (tcr) offset 0dh (write) field name description 7 fdu full duplex : this bit indicates the current media mode is full duplex or not. 0 : half duplex 1 : full duplex 6 pd pad disable 0 : pad will be added when packet length less than 60. 1 : pad will not be added when packet length less tha n 60. 5 rlo retry of late collision 0 : don ? t retransmit packet when late collision happens. 1 : retransmit packet when late collision happens. 4:3 - reserved 2:1 lb1,lb0 encoded loop-back control these encoded configuration bits set the type of loop-back that is to be performed. lb1 lb0 mode 0 0 0 normal operation mode 1 0 1 internel nic loop-back mode 2 1 0 phycevisor loop-back 0 crc inhibit crc 0 : crc appended by transmitter. 1 : crc inhibited by transmitter.
ax88196 local cpu bus mac controller asix electronics corporation 20 4.6 transmit status register (tsr) offset 04h (read) field name description 7 owc out of window collision 6:4 - reserved 3 abt transmit aborted indicates the ax88196 aborted transmission because of excessive collision. 2 col transmit collided indicates that the transmission collided at least once with another station on the network. 1 - reserved 0 ptx packet transmitted indicates transmission without error. 4.7 receive configuration (rcr) offset 0ch (write) field name description 7 - reserved 6 intt interrupt tri g ger mode for isa and 80186 modes 0 : low active 1 : high active (default) interrupt tri g ger mode for mcs-51 and mc68k modes 0 : high active 1 : low active (default) 5 mon monitor mode 0 : normal operation 1 : monitor mode, the input packet will be checked on node address and crc but not buffered into memory. 4 pro pro : promiscuous mode enable the receiver to accept all packets with a physical address. 3 am am : accept multicast enable the receiver to accept packets with a multicast address. that multicast address must pass the hashing array. 2 ab ab : accept broadcast enable the receiver to accept broadcast packet. 1 ar ar : accept runt enable the receiver to accept runt packet. 0 sep sep : save error packet enable the receiver to accept and save packets with error. 4.8 receive status register (rsr) offset 0ch (read) field name description 7 - reserved 6 dis receiver disabled 5 phy multicast address received. 4 mpa missed packet 3 fo fifo overrun 2 fae frame alignment error. 1 cr crc error. 0 prx packet received intact
ax88196 local cpu bus mac controller asix electronics corporation 21 4.9 inter-frame gap (ifg) offset 16h (read/write) field name description 7 - reserved 6:0 ifg inter-frame gap . default value 15h. 4.10 inter-frame gap segment 1 ( ifgs1 ) offset 12h (read/write) field name description 7 - reserved 6:0 ifg inter-frame gap segment 1 . default value 0ch. 4.11 inter-frame gap segment 2 ( ifgs2 ) offset 13h (read/write) field name description 7 - reserved 6:0 ifg inter-frame gap segment 2 . default value 11h. 4.12 mii/eeprom management register ( memr ) offset 14h (read/write) field name description 7 eeclk eeclk eeprom clock 6 eeo eeo eeprom data out 5 eei eei eeprom data in 4 eecs eecs eeprom chip select 3 mdo mdo mii data out 2 mdi mdi mii data in 1 m dir mii sta mdio signal direction mii read control bit, assert this bit let mdio signal as the input signal. deassert this bit let mdio as output signal. 0 mdc mdc mii clock 4.13 test register (tr) offset 15h (write) field name description 7 - reserved 6 mpsel media priority select : default value is logic 0 mpsel /slink media selected 0 0 sni 0 1 mii 1 x depand on mpset bit 5 mpset media set by program : the signal is valid only when mpsel is set to high. when mpset is logic 0 , sni is selected. when mpset is logic 1 , mii is selected. 4 tf16t test for collision, default value is logic 0 3 tpe test pin enable , default value is logic 0 2:0 ifg select test pins output , default value is logic 0
ax88196 local cpu bus mac controller asix electronics corporation 22 4.14 spp data port register ( spp_dp r) offset 18h (read/write) field name description 7:0 dp printer data port 4.15 spp status port register ( spp_sp r) offset 19h (read) field name description 7 /busy reading a ? 0 ? indicates that the printer is not ready to receive new data. 6 /ack reading a ? 0 ? indicates that the printer has received the data and is ready to accept new data. 5 pe reading a ? 1 ? indicates that the printer is out of paper. 4 slct reading a ? 1 ? indicates that the printer has power on. 3 /err reading a ? 0 ? indicates that there is an error condition at the printer. 2:0 - reserved 4.16 spp command port register ( spp_cp r) offset 1ah (read/write) field name description 7:6 - reserved 5 /doe seting to ? 0 ? enable print data output to printer. default sets to ? 1 ? . 4 irqen irq enable : printer port interrupt is not supportted. 3 slctin seting to ? 1 ? selects the printer. 2 /init seting to ? 0 ? initiates the printer 1 atfd seting to ? 1 ? causes the printer to automatically feed one line after each line is printed. 0 strb seting a low-high-low pulse on this register is used to strobe the print data into the printer.
ax88196 local cpu bus mac controller asix electronics corporation 23 5.0 cpu i/o read and write functions the ax88196 supports four kinds of cpu/bus types access function, including isa, 80186, mc68000 and mcs- 51. these access methods are described as the following sections. 5.1 isa bus type access functions. isa bus i/o read function function mode /cs /bhe a0 /iord /iowr sd[15:8] sd[7:0] standby mode h x x x x high-z high-z byte access l l h h l h l l h h not valid not valid even-byte odd-byte word access l l l l h odd-byte even-byte isa bus i/o write function function mode /cs /bhe a0 /iord /iowr sd[15:8] sd[7:0] standby mode h x x x x x x byte access l l h h l h h h l l x x even-byte odd-byte word access l l l h l odd-byte even-byte 5.2 80186 cpu bus type access functions. 80186 cpu bus i/o read function function mode /cs /bhe a0 /iord /iowr sd[15:8] sd[7:0] standby mode h x x x x high-z high-z byte access l l h l l h l l h h not valid odd-byte even-byte not valid word access l l l l h odd-byte even-byte 80186 cpu bus i/o write function function mode /cs /bhe a0 /iord /iowr sd[15:8] sd[7:0] standby mode h x x x x x x byte access l l h l l h h h l l x odd-byte even-byte x word access l l l h l odd-byte even-byte
ax88196 local cpu bus mac controller asix electronics corporation 24 5.3 mc68k cpu bus type access functions. 68k bus i/o read function function mode /cs /uds /lds r/w sd[15:8] sd[7:0] standby mode h x x x high-z high-z byte access l l h l l h h h not valid even-byte odd-byte not valid word access l l l h even-byte odd-byte 68k bus i/o write function function mode /cs /uds /lds r/w sd[15:8] sd[7:0] standby mode h x x x x x byte access l l h l l h l l x even-byte odd-byte x word access l l l l even-byte odd-byte 5.4 mcs-51 cpu bus type access functions. 8051 bus i/o read function function mode /cs /psen sa0 /iord /iowr sd[15:8] sd[7:0] standby mode h x x l x x x x x x high-z high-z high-z high-z byte access l l h h l h l l h h not valid not valid even-byte odd-byte 8051 bus i/o write function function mode /cs /psen sa0 /iord /iowr sd[15:8] sd[7:0] standby mode h x x l x x x x x x x x x x byte access l l h h l h h h l l x x even-byte odd-byte
ax88196 local cpu bus mac controller asix electronics corporation 25 6.0 electrical specification and timings 6.1 absolute maximum ratings description sym min max units operating temperature ta 0 +85 c storage temperature ts -55 +150 c supply voltage hvdd -0.3 +6 v supply voltage lvdd -0.3 +4.6 v input voltage hvin lvin -0.3 -0.3 hvdd+0.5 lvdd+0.5 v v output voltage hvout lvin -0.3 -0.3 hvdd+0.5 lvdd+0.5 v v lead temperature (soldering 10 seconds maximum) tl -55 +220 c note : stress above those listed under absolute maximum ratings may cause permanent damage to the device. exposure to absolute maximum ratings conditions for extended period, adversely affect device life and reliability. note : the power supply voltages must always fulfill hvdd >= lvdd inequality. 6.2 general operation conditions description sym min tpy max units operating temperature ta 0 25 +75 c supply voltage hvdd lvdd +4.75v +2.70 +3.00 +5.00v +3.00 +3.30 +5.25v +3.30 +3.60 v v v note : the power supply voltages must always fulfill hvdd >= lvdd inequality. 6.3 dc characteristics (vdd=5.0v, vss=0v, ta=0 c to 75 c) description sym min tpy max units low input voltage vil - 0.8 v high input voltage vih 2 - v low output voltage vol - 0.4 v high output voltage voh vdd-0.4 - v input leakage current iil -1 +1 ua output leakage current iol -1 +1 ua (vdd=3.0v to 3.6v, vss=0v, ta=0 c to 75 c) description sym min tpy max units low input voltage vil - 0.8 v high input voltage vih 1.9 - v low output voltage vol - 0.4 v high output voltage voh vdd-0.4 - v input leakage current iil -1 +1 ua output leakage current iol -1 +1 ua description sym min tpy max units power consumption (dual power) dpt5v dpt3v 20 32 ma ma power consumption (single power 3.3v) spt3v 50 ma
ax88196 local cpu bus mac controller asix electronics corporation 26 6.4 a.c. timing characteristics 6.4.1 xtal / clock lclk/xtalin tr tf tlo w clko tod symbol description min typ. max units t cyc cycle time 40* ns t high clk high time 16 20 24 ns t low clk low time 16 20 24 ns t r/ t f clk slew rate 1 - 4 ns tod lclk/xtalin to clko out delay 10 * note : the tcyc can be from 16.6ns to 50ns, that is frequency from 60mhz to 20mhz. 6.4.2 reset timing lclk /xtalin reset /reset symbol description min typ. max units trst reset pulse width 100 - - lclk tcyc thigh
ax88196 local cpu bus mac controller asix electronics corporation 27 6.4.3 isa bus access timing tsu(aen) th(aen) aen tsu(a) th(a) /bhe sa[9:0],sal,sah tv(cs16-a) tdis(cs16-a) /iocs16 ten(rd) /iowr,/iord tv(rdy) tdis(rdy) rdy tdis(rd) read data sd[15:0](dout) data valid tsu(wr) th(wr) write data sd[15:0](din) data input establish symbol description min typ. max units t su(a) address setup time 0 - - ns t h(a) address hold time 5 - - ns t su(aen) aen setup time 0 - - ns t h(aen) aen hold time 5 - - ns t v(cs16-a) /iocs16 valid from address change - - 20 ns t dis(cs16-a) /iocs16 disable from address change - - 6 ns t v(rdy) rdy valid from /iord or /iowr - - 20 ns t dis(rdy) rdy disable from /iord or /iowr 0 - - ns t en(rd) output enable time from /iord - - 20 ns t dis(rd) output disable time from /iord 0.5 - 4 ns t su(wr) data setup time 5 - - ns t h(wr) data hold time 5 - - ns
ax88196 local cpu bus mac controller asix electronics corporation 28 6.4.4 80186 type i/o access timing tsu(a) th(a) /bhe sa[9:0],sal,sah tw(rw) /iowr,/iord tv(rdy) tdis(rdy) rdy ten(rd) tdis(rd) read data sd[15:0](dout) data valid tsu(wr) th(wr) write data sd[15:0](din) data input establish symbol description min typ. max units t su(a) address setup time 0 - - ns t h(a) address hold time 5 - - ns t v(rdy) rdy valid from /iord or /iowr - - 20 ns t dis(rdy) rdy disable from /iord or /iowr 0 - - ns t en(rd) output enable time from /iord - - 20 ns t dis(rd) output disable time from /iord 0.5 - 4 ns t su(wr) data setup time 5 - - ns t h(wr) data hold time 5 - - ns tw(rw) /iord or /iowr width time *60 ns *note : 60 ns at internal operation clock is 20mhz. 50 ns at internal operation clock is 25mhz.
ax88196 local cpu bus mac controller asix electronics corporation 29 6.4.5 68k type i/o access timing tsu(a) th(a) sa[9:1],sal,sah tv(ds-wr) tw(ds) tdis(wr-ds) /uds,/lds (read) r/w ten(ds) (write) r/w tv(dtack) tdis(dtack) /dtack tdis(ds) (read data) sd[15:0](dout) data valid tsu(ds) th(ds) (write data) sd[15:0](din) data input establish symbol description min typ. max units t su(a) address setup time 0 - - ns t h(a) address hold time 5 - - ns t v(ds-wr) /uds or /lds valid from /w 0 - - ns t dis(wr-ds) /w disable from /uds or /lds 5 - - ns t v(dtack) dack valid from /uds or /lds - - 20 ns t dis(dtack) dack disable from /uds or /lds 0 - - ns t en(ds) output enable time from /uds or /lds - - 20 ns t dis(ds) output disable time from /uds or /lds 0.5 - 4 ns t su(ds) data setup time 5 - - ns t h(ds) data hold time 5 - - ns tw(ds) /uds or /lds width time *60 ns *note : 60 ns at internal operation clock is 20mhz. 50 ns at internal operation clock is 25mhz.
ax88196 local cpu bus mac controller asix electronics corporation 30 6.4.6 8051 bus access timing /psen tsu(psen) th(psen) tsu(a) th(a) sa[9:0],sal,sah ten(rd) /iowr,/iord tw(rw) tv(rdy) tdis(rdy) (for reference) rdy tdis(rd) read data sd[7:0](dout) data valid tsu(wr) th(wr) write data sd[7:0](din) data input establish symbol description min typ. max units t su(a) address setup time 0 - - ns t h(a) address hold time 5 - - ns t su(psen) /psen setup time 0 - - ns t h(psen) /psen hold time 5 - - ns t en(rd) output enable time from /iord - - 20 ns t dis(rd) output disable time from /iord 0.5 - 4 ns t su(wr) data setup time 5 - - ns t h(wr) data hold time 5 - - ns tw(rw) /iord or /iowr width time *60 ns note : 60 ns at internal operation clock 20mhz. 50 ns at internal operation clock 25mhz.
ax88196 local cpu bus mac controller asix electronics corporation 31 6.4.7 mii timing ttclk ttch ttcl txclk ttv tth txd<3:0> txen trclk trch trcl rxclk trs trh rxd<3:0> rxdv trs1 rxer symbol description min typ. max units ttclk cycle time(100mbps) - 40 - ns ttclk cycle time(10mbps) - 400 - ns ttch high time(100mbps) 14 - 26 ns ttch high time(10mbps) 140 - 260 ns trch low time(100mbps) 14 - 26 ns trch low time(10mbps) 140 - 260 ns ttv clock to data valid - - 20 ns tth data output hold time 5 - - ns trclk cycle time(100mbps) - 40 - ns trclk cycle time(10mbps) - 400 - ns trch high time(100mbps) 14 - 26 ns trch high time(10mbps) 140 - 260 ns trcl low time(100mbps) 14 - 26 ns trcl low time(10mbps) 140 - 260 ns trs data setup time 6 - - ns trh data hold time 10 - - ns trs1 rxer data setup time 10 - - ns
ax88196 local cpu bus mac controller asix electronics corporation 32 6.4.8 sni timing ttclk ttch ttcl stxc ttv tth stxd stxe trclk trch trcl srxc trs trh srxd scrs symbol description min typ. max units ttclk cycle time(10mbps) - 100 - ns ttch high time(10mbps) 45 - 55 ns trch low time(10mbps) 45 - 55 ns ttv clock to data valid - - 26 ns tth data output hold time 5 - - ns trclk cycle time(10mbps) - 100 - ns trch high time(10mbps) 45 - 55 ns trcl low time(10mbps) 45 - 55 ns trs data setup time 10 - - ns trh data hold time 5 - - ns
ax88196 local cpu bus mac controller asix electronics corporation 33 7.0 package information b e d hd e he pin 1 a2 a1 l l1 q a milimeter symbol min. nom max a1 0.1 a2 1.3 1.4 1.5 a 1.7 b 0.155 0.16 0.26 d 13.90 14.00 14.10 e 13.90 14.00 14.10 e 0.40 hd 15.60 16.00 16.40 he 15.60 16.00 16.40 l 0.30 0.50 0.70 l1 1.00 q 0 10
ax88196 local cpu bus mac controller asix electronics corporation 34 appendix a: application note a.1 using crystal 25mhz or 20mhz ax88196 to phy clko 25mhz xtalin xtalout 25mhz crystal 8pf 2mohm 8pf note : the capacitors (8pf) may be various depend on the specification of crystal. while designing, please refer to the suggest circuit provided by crystal supplier. a.2 using oscillator 25mhz or 20mhz ax88190a to phy clko 20mhz xtalin xtalout nc 3.3v power osc 20mhz a.3 using 60mhz oscillator/crystal ax88196 to phy clko 60mhz /clk_div3 pull low 20mhz xtalin xtalout nc 3.3v power osc 60mhz devided by 3
ax88196 local cpu bus mac controller asix electronics corporation 35 a.4 dual power (5v and 3.3v/3.0v) application +5v +5v +5v hvdd +5v +3.3v lvdd a.5 single power (3.3v/3.0v) application +3.3v +3.3v +3.3v hvdd +3.3v +3.3v lvdd ax88196 phy/txrx magnetic rj45 +5v cpu i/f optional eeprom ax88196 phy/txrx magnetic rj45 +3.3v cpu i/f optional eeprom
ax88196 local cpu bus mac controller asix electronics corporation 36 a.6 dual power (5v and 3.3v) application with 3.3v phy the 510 and 1k ohm resisters are just for voltage adjustment ax88196 phy rxd[3:0] crs rx_dv rx_er rx_clk col tx_en txd[3:0] tx_clk mdc mdio rxd[3:0] crs rx_dv rx_er rx_clk col tx_en txd[3:0] tx_clk mdc mdio 510 ohm 1k ohm
ax88196 local cpu bus mac controller asix electronics corporation 37 errata of ax88196 version ed2 1. sni (serial network interface) has bug for homepna application. solution: using mii interface for homepna solution. refer to ? demonstration circuit ? on page 37 to 41. 2. spp command port readback value is from internal registers instead of external pins solution: asix will not fix the problem at this moment. care must be taken when doing the external pins diagnostic. 3. dtack can ? t fit 68k cpu timing in 68k mode solution : using the dtack automatic insertion function in 68k cpu.
ax88196 10 /100base fast ethernet mac controller asix electronics corporation 38 demonstration circuit : ax88196 + ethernet phy + homepna 1m8 phy c5 0.1u c8 0.1u sd0 u1b 74hc04 3 4 sd10 rst1# u1a 74hc04 1 2 5v sd9 5v 3.3v iocs16# sd5 5v sa9 + c6 47u/16v c10 0.1u + c1 47u/16v u1c 74hc04 5 6 196ns2a.sch 1.1 isa bus asix electronics corporation a 1 5 thursday, september 21, 2000 title size document number rev date: sheet of + c11 47u/16v gnd irq7 sa2 c7 0.1u sa7 reset sa6 u1e 74hc04 11 10 sa[0..9] sa3 irq5 sd15 c2 0.1u irq7 sd12 u2 lt1086 1 2 3 4 adj/gnd out in out + c9 47u/16v sd13 iowr# sd2 ax88196 l 10base-t/100base-tx & 1m homepna application with dp83846 & dp83851 (for isa mode)(reference only) sd8 5v 3.3v sa8 iord# vcc irq bhe# 5v sa5 sa0 rst2# gnd sd6 jp1 jump 1 3 5 7 9 2 4 6 8 10 c4 0.1u rdy sa4 + c3 47u/16v gnd sd3 u1f 74hc04 13 12 u1d 74hc04 9 8 gnd isa1 isa a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 a16 a17 a18 a19 a20 a21 a22 a23 a24 a25 a26 a27 a28 a29 a30 a31 c1 c2 c3 c4 c5 c6 c7 c8 c9 c10 c11 c12 c13 c14 c15 c16 c17 c18 b1 b2 b3 b4 b5 b6 b7 b8 b9 b10 b11 b12 b13 b14 b15 b16 b17 b18 b19 b20 b21 b22 b23 b24 b25 b26 b27 b28 b29 b30 b31 d1 d2 d3 d4 d5 d6 d7 d8 d9 d11 d12 d13 d14 d15 d16 d17 d18 d10 iochk# d<7> d<6> d<5> d<4> d<3> d<2> d<1> d<0> chrdy aen sa<19> sa<18> sa<17> sa<16> sa<15> sa<14> sa<13> sa<12> sa<11> sa<10 sa<9> sa<8> sa<7> sa<6> sa<5> sa<4> sa<3> sa<2> sa<1> sa<0> sbhe# la<23> la<22> la<21> la<20> la<19> la<18> la<17> mrdc# mwtc# d<8> d<9> d<10> d<11> d<12> d<13> d<14> d<15> gnd resdrv +5v irq<9> -5v drq<2> -12v nows# +12v gnd smwtc# smrdc lowc# lorc# dak<3># drq<3> dak<1># drq<1> refrsh# bclk irq<7> irq<6> irq<5> irq<4> irq<3> dak<2># t/c bale +5v osc gnd m16# io16# irq<10> irq<11> irq<12> irq<13> irq<14> dak<0># drq<0> drq<5> dak<6># drq<6> dak<7># drq<7> +5v master16# gnd dak<5># aen reset irq3 sd7 5v sa1 sd11 sd4 sd1 irq5 gnd 5v sd14 irq3 irq11 gnd sd[0..15] jp1 is setting irq reset irq11 irq12 irq12
ax88196 10 /100base fast ethernet mac controller asix electronics corporation 39 sd15 sd14 mdc sd6 c26 0.1u bhe# 0 sa6 + c15 47u/16v col crs r4 10k aen sd13 3a0h mc68k sd5 0 0 c19 0.1u c20 0.1u 8051 0 0 r3 10k r5 10k 3.3v r6 10k txd3 cpu0 xin sa[0..9] iord# rxd1 sd12 rxd0 0 txen isa bus c23 0.1u u4 93c56 1 2 3 4 5 6 7 8 cs sk di do gnd nc nc vcc c22 0.1u 0 c14 8p sd11 5v r1 20 iobase2 1 rxd2 1 xin c16 0.1u iobase0 c24 0.1u sd9 sd7 sa7 c25 0.1u sa9 cpu0 0 0 sa3 5v 1 gnd sd4 sd3 25mhz option sa5 iocs16# 1 380h sa1 sd0 j1 io/base select 1 3 5 2 4 6 sd2 eedo 220h 1 5v 360h 1 0 1 cpu type & io base select eecs xout c13 8p 1 1 1 196ns2a1.sch 1.1 ax88195 mac controll asix electronics corporation b 2 5 thursday, september 21, 2000 title size document number rev date: sheet of y1 25mhz-crystal 1 gnd 0 1 rxd3 0 r7 10k txck 0 gnd eedo io base cpu1 1 eedi gep1 1 c12 0.1u iobase0 mode 80186 irq rxck iobase1 reset rxer mdio 300h eedi r2 2m c27 0.1u 0 rxdv sd10 r8 10k 320h rdy 1 eesk eecs xout iobase2 0 sa8 iobase1 gep0 sa4 c17 0.1u sd8 u3 ax88196 1 2 3 4 5 6 7 8 9 10 11 12 14 15 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 69 71 72 74 75 77 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 119 120 123 124 125 126 127 128 sa<0> /uds sa<1> sa<2> sa<3> sa<4> sa<5> sa<6> sa<7> sa<8> sa<9> vss irq /irq /iowr r/w /iord /bhe /lds hvdd sd<15> sd<14> sd<13> sd<12> vss sd<11> sd<10> sd<9> sd<8> hvdd sd<7> sd<6> sd<5> sd<4> vss sd<3> sd<2> sd<1> sd<0> vss /slin /init /atfd lvdd /strb busy /ack pe vss slct /err pd7 pd6 lvdd pd5 pd4 pd3 pd2 vss pd1 gep1 pd0 gep0 io_base<2> io_base<1> hvdd io_base<0> vss cpu<1> cpu<0> /slink hvdd test vss rx_er rx_dv col crs rx_clk rxd<0> rxd<1> rxd<2> rxd<3> mdio mdc vss tx_clk tx_en txd<0> txd<1> txd<2> txd<3> lvdd clko25m vss lclk/xtalin xtalout vss eecs eeck eedi eedo lvdd sal<0> sal<1> sal<2> sah<0> sah<1> sah<2> vss /iocs16 /cs aen/psen rdy/dtack /reset reset lvdd 3.3v 0 c18 0.1u 340h 200h eesk txd0 sa2 sa0 sd1 txd1 + c21 47u/16v r9 10k iowr# sd[0..15] cpu1 txd2 1
ax88196 10 /100base fast ethernet mac controller asix electronics corporation 40 rdp 3.3v c29 10p 3.3v u5 hr008 5 4 3 2 1 7 8 6 12 13 14 15 16 11 10 9 td+ td- ct_td rd+ rd- hrtrxp+ hrtrxn- gnd tx+ tx- nc2 rx+ rx- nc1 ring tip tdn ring r17 49.9 1% r13 75 3.3v c28 0.1u gnd tdn c31 10p rdn tip transmit 1ct : 1ct rx 1ct : 1ct homepna 1ct : 1ct r12 75 c32 0.01u/2kv r15 49.9 1% r16 49.9 1% tdp gnd_ch tdp j2 rj45n 1 2 3 6 4 5 7 8 u6 dual-rj11-6p 1 2 3 4 5 6 7 8 9 10 11 12 nc a1 tip_a ring_a a2 nc nc b1 tip_b ring_b b2 nc c34 0.01u c30 10p r14 49.9 1% c35 0.1u c33 0.1u rdn r11 49.9 1% r10 49.9 1% gnd_ch 196ns2a4.sch 1.1 rj45 & rj11 asix electronics corporation a 3 5 thursday, september 21, 2000 title size document number rev date: sheet of tip rdp ring
ax88196 10 /100base fast ethernet mac controller asix electronics corporation 41 colled txd1 u7 dp83851b 36 35 34 33 32 31 23 24 25 26 27 28 37 38 21 22 45 46 19 29 39 5 11 20 7 8 4 17 18 16 15 44 14 42 43 48 30 40 41 47 3 6 10 1 2 9 12 13 txd3 txd2 txd1 txd0/txd tx_en tx_clk rxd3/phyad0 rxd2/cmddis# rxd1/hi_power_en# rxd0/rxd/low_speed_en# rx_dv/gpsi_sel# rx_clk col/mdio_int_en# crs/pin_intrp_en# mdio mdc x1 x2 io_vdd1 io_vdd2 core_vdd ana_vdd2 ana_vdd3 io_gnd1 tip ring rbias led_col/phyad2 led_act/phyad1 led_speed/phyad3 led_power/phyad4 reset# reserved reserved reserved ana_vdd1 io_gnd2 core_gnd core_sub(0v) ana_gnd1 ana_gnd2 ana_gnd3 ana_gnd4 sub_gnd1 sub_gnd2 sub_gnd3 reserved reserved tip l1 f.b. rxdv d1 led 3.3v activity led r29 510 pwrled rxd2 mdio r18 20 rxdv txen c41 0.1u r22 4.7k c44 0.1u c43 0.1u colled actled rxd1 r27 510 ring col d3 led crs r21 9.31k 1% txd3 r20 4.7k rxck txd0 3.3v speed led txd0 196ns2a2.sch 1.1 dp83851b homepna phyceiver a4 4 5 thursday, september 21, 2000 asix electronics corporation title size document number rev date: sheet of rxd3 txck r23 4.7k rxd0 reset# rxd3 txen rst1# 3.3v txd2 cillision led c39 0.1u spdled gnd rxd3 c37 0.1u ring + c36 47uf/16v colled rxd2 actled rxd1 spdled rxd0 r19 20 crs mdc actled txd1 r25 4.7k c38 0.1u 25mhz pwrled r26 4.7k gnd tip 3.3va2 pclk c40 0.1u txd2 c42 0.1u l2 f.b. set phy address to 00000. r24 4.7k r28 510 d2 led col spdled txd3 mdio 3.3v 3.3va1 3.3v mdc
ax88196 10 /100base fast ethernet mac controller asix electronics corporation 42 c47 0.1u 3.3v mdc reset# txd2 c49 0.1u r42 510 u8 dp83846a 59 58 55 54 52 51 38 39 40 41 44 45 60 61 36 37 67 66 57 65 12 14 64 3 7 23 73 2 9 13 15 18 19 76 79 50 46 16 17 11 10 1 5 8 20 21 22 47 63 68 69 70 71 74 75 77 78 80 6 48 34 42 53 56 4 24 49 72 43 35 62 33 32 31 30 29 28 27 26 25 txd3 txd2 txd1 txd0 tx_en tx_clk rxd3 rxd2 rxd1 rxd0 rx_dv rx_clk col crs/led_cfg# mdio mdc x1 x2 io_vdd io_vdd ana_vdd2 ana_vdd3 io_gnd rbias ana_vdd1 core_gnd core_gnd ana_gnd ana_gnd ana_gnd ana_gnd ana_gnd sub_gnd sub_gnd sub_gnd tx_er rx_er/pause_en# td+ td- rd+ rd- reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved ana_gnd core_gnd io_gnd io_gnd io_gnd io_gnd ana_vdd core_vdd core_vdd core_vdd io_vdd io_vdd reset# led_dplx/phy0 led_col/phy1 led_gdlnk/phy2 led_tx/phy3 led_rx/phy4 led_speed an_en an_1 an_0 fled phyad4 rled rxd1 3.3v r35 4.7k lled pclk c46 0.1u rled rxd1 rxdv rxd0 rxd3 c51 0.1u rxdv transmit activity : used r42. receive activity : used r44. transmit/receive activity : d6 & d8 & r43. txen crs l4 f.b. tdn r40 510 tled d4 led r36 4.7k tdp phyad2 txd1 d7 led fled txen c54 0.1u rled r43 510 tled tled crs l3 f.b. d5 led + c45 47uf/16v r39 4.7k r31 20 set phy address to 00011 r32 20 r37 4.7k col rdn c52 0.1u cled lled col r38 9.31k rst2# 25mhz link led r33 4.7k txck mdc rdn rdp rxd3 r34 4.7k txd0 3.3va1 gnd rxck 196ns2a3.sch 1.1 dp83846a a4 5 5 thursday, september 21, 2000 asix electronics corporation title size document number rev date: sheet of rdp phyad0 sled txd3 gnd d8 1n4148 phyad3 3.3v r44 510 c53 0.1u txd1 cled rxer txd3 3.3v d6 1n4148 rxer mdio tdn mdio 3.3va2 gnd c48 0.1u rxd2 tdp r41 510 phyad1 txd2 c50 0.1u activity led speed led lled 3.3v rxd0 sled txd0 3.3v r30 20 rxd2

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